The invention relates to an integrated matrix of nonvolatile, reprogrammable storage cells of which one section serves as a redundant memory, or in which a redundant memory is provided. The rows of the redundant memory replace defective matrix rows whose addresses, subsequently to the testing of the matrix, are stored in a read-only memory (ROM) and in correcting (patch) registers of the static, volatile storage cells. During the operational occurrence of addresses associated with defective matrix rows, the corresponding rows of the redundant memory are activated and the defective matrix rows are blocked.
Accordingly, the invention deals with so-called redundant memories in which the number of storage cells exceeds the number of actually required storage cells. As a result, unserviceable, or defective storage cells can be replaced by the redundant storage cells. The invention is based on a prior art as disclosed in the technical journal "IEEE Journal of Solid-State Circuits," October 1978, pp. 698 to 703, in particular page 699, left-hand column. Of the three possibilities disclosed therein, for storing the addresses of the defective storage cells only the first, namely the use of static, volatile storage cells (referred to in the prior art publication as "electrically alterable latches") is of interest here. Relative to this storage variety it is stated that, owing to the volatility of this type of storage, the addresses of the defective storage cells must additionally be contained in a read-only memory. In the aforementioned publication, a magnetic "disk" memory is provided.
With a view to the integrated manufacture of such storage matrices, however, the use of magnetic storage disks represents a technique which is incompatible with the semiconductor technology. It is a basic requirement, therefore, that the functions of such a redundant memory are to be realized by employing integrated semiconductor circuit technology. It appears to be prohibitive to use magnetic disks for fixedly storing the addresses of defective storage cells if as much integration as possible is to be achieved.
The invention solves the problem of designing a redundant storage matrix by exclusively employing the means customary in semiconductor technology. Special techniques, such as the use of blowable resistors or components capable of being trimmed or adjusted with the aid of lasers referred to in the aforementioned prior art publication, as special processes, are excluded as they are only compatible with standard integrated technology by making increased investments. In fact, such special processes require an additional and considerable investment in apparatus. Especially when realizing such storage matrices on as small as possible surface area with small conductor widths and spacings, such special processes cause quite a number of difficulties.